The present invention relates to interconnect structures for electrically connecting vertically arranged circuit boards.
Examples of prior art structures are shown in U.S. Pat. Nos. 4,283,755; 3,591,834; 3,489,954; 3,459,998 and 3,418,533.
Conventionally, in order for one board to "talk" to an adjacent overlying or underlying board, signal lines are run from the chips of the first board to the edge of the board, conductors are then provided from the edge of the first board to the edge of the second board, and signal lines then connect the conductors along the edge of the second board to the chips of the second board.
While the prior art evidences some progress in improving upon this circuitous route for board to board signal lines, none of the prior art structures discloses an interconnect structure which suitably solves the board to board interconnect problem, especially for boards carrying many chips. Moreover, in the past, the "well space" directly underlying each of the chips, and generally bounded by its pin arrangement, has been ignored as an interconnect region, wasting valuable circuit board space.